VLSI mini and major project best in 2020
VLSI Mini and major project for ECE 2019 to 2020
1. Reconfigurable Constant Multiplication for FPGAs
2. Design of Power and Area Efficient Approximate Multipliers
3. Multipliers-Driven Perturbation of Coefficients for Low-Power Operation in Reconfigurable FIR Filters
4. A Computationally Efficient Reconfigurable Constant Multiplication Architecture Based on
5. CSD Decoded Vertical–Horizontal Common Sub-Expression Elimination Algorithm
6. Design of Low Power 8-Bit Carry Select Adder Using Adiabatic Logic
7. Hardware Design of an Energy-Efficient High-Throughput Median Filter
8. VLSI Implementation of 3D Integer DCT for Video Coding Standards
9. Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication
10. Pre-Encoded Multipliers Based on Non-Redundant Radix-4 Signed-Digit Encoding
11. Delay Efficient Error Detection and Correction of Parallel IIR Filters using VLSI Algorithms
12. Addition of Miller and Inverted Manchester Encoding Technique to Dedicated Short Range Communication with Full Hardware Utilization
13. Carry Speculative Adder with Variable Latency for Low Power VLSI
14. A New VLSI Algorithm for a High-Throughput Implementation of Type IV DCT
15. Design and Implementation of 64 Bit Multiplier using Vedic Algorithm
16. A 0.3-V 37-nW 53-dB SNDR Asynchronous Delta–Sigma Modulator in 0.18-μm CMOS
17. Exploiting Algorithmic Noise Tolerance for Scalable On-Chip Voltage Regulation
18. Low-Power Near-Threshold 10T SRAM Bit Cells With Enhanced Data-Independent Read Port Leakage for Array Augmentation in 32-nm CMOS
19. Radiation-Hardened 14T SRAM Bitcell With Speed and Power Optimized for Space Application
20. An Accurate and Noise-Resilient Spread-Spectrum Clock Tracking Aid for Digitally-Controlled Clock and Data Recovery Loops
21. VLSI Design of an ML-Based Power-Efficient Motion Estimation Controller for Intelligent Mobile Systems
22.Fast Neural Network Training on FPGA Using Quasi-Newton Optimization Method
23.
1. Reconfigurable Constant Multiplication for FPGAs
2. Design of Power and Area Efficient Approximate Multipliers
3. Multipliers-Driven Perturbation of Coefficients for Low-Power Operation in Reconfigurable FIR Filters
4. A Computationally Efficient Reconfigurable Constant Multiplication Architecture Based on
5. CSD Decoded Vertical–Horizontal Common Sub-Expression Elimination Algorithm
6. Design of Low Power 8-Bit Carry Select Adder Using Adiabatic Logic
7. Hardware Design of an Energy-Efficient High-Throughput Median Filter
8. VLSI Implementation of 3D Integer DCT for Video Coding Standards
9. Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication
10. Pre-Encoded Multipliers Based on Non-Redundant Radix-4 Signed-Digit Encoding
11. Delay Efficient Error Detection and Correction of Parallel IIR Filters using VLSI Algorithms
12. Addition of Miller and Inverted Manchester Encoding Technique to Dedicated Short Range Communication with Full Hardware Utilization
13. Carry Speculative Adder with Variable Latency for Low Power VLSI
14. A New VLSI Algorithm for a High-Throughput Implementation of Type IV DCT
15. Design and Implementation of 64 Bit Multiplier using Vedic Algorithm
16. A 0.3-V 37-nW 53-dB SNDR Asynchronous Delta–Sigma Modulator in 0.18-μm CMOS
17. Exploiting Algorithmic Noise Tolerance for Scalable On-Chip Voltage Regulation
18. Low-Power Near-Threshold 10T SRAM Bit Cells With Enhanced Data-Independent Read Port Leakage for Array Augmentation in 32-nm CMOS
19. Radiation-Hardened 14T SRAM Bitcell With Speed and Power Optimized for Space Application
20. An Accurate and Noise-Resilient Spread-Spectrum Clock Tracking Aid for Digitally-Controlled Clock and Data Recovery Loops
21. VLSI Design of an ML-Based Power-Efficient Motion Estimation Controller for Intelligent Mobile Systems
22.Fast Neural Network Training on FPGA Using Quasi-Newton Optimization Method
23.
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- Design and Implementation of Efficient Systolic Array Architecture:
- To objective of this project is to develop a hardware model of systolic array multiplier which can be used to perform binary multiplication using VHDL platform. This design is implemented on FPGA and simulated in Isim software.
- VHDL Environment for Floating Point Arithmetic Logic Unit : This project aims to design and simulate the pipeline approach based floating point ALU using VHDL. This pipelining approach allows the multiple instructions to execute simultaneously.
- Design and Implementation of High Speed DDR SDRAM Controller: This project implements a burst data transfer based high speed DDR SDRAM controller that synchronizes the transfer of data between DDR SDRAM and the rest of embedded system circuitry. This code is developed by using VHDL.
- Design and Synthesis of QPSK: In this project, one of the popular modulation technique used in satellite radio applications i.e., QPSK modulation is implemented by using reversible logic gates. This modulation technique is modeled using VHDL code.
- Design of Multi Value Logic Using Quantum Dot Gate FET: This project aims to increase the bit handling capacity of logic circuits by designing a circuit model of three-stage quantum dot gate field effect transistors (QDGFETs). This three stage design is implemented for different combinational circuits like comparator and decoder.
- Design and Simulation of FFT Processor Using Radix-4 Algorithm Using FPGA: This project simulates and synthesizes the 256-point Fast Fourier Transform (FFT) processor with Radix-4 algorithm which is popularly used in WLAN and Orthogonal Frequency Division Multiplexer (OFDM). This project is designed by using VHDL coding.
- Design and Implementation of 32 – bit RISC Processor: The main objective of this paper is to implement a 32 bit Reduced Instruction Set Computer (RISC) using XILINK VIRTEX4 tool. In this design 16 set instructions are designed where each instruction is executed in one clock cycle with 5 stage pipelining technique.
- VHDL Model of Smart Sensor: The aim of this project is to build a VHDL model of smart sensor by implementing algorithm for smart sensor with noise cancellation using IEEE 1451 communication standard. The complete simulation of this project is carried by VHDL program.
- Fuzzy based PID Controller using VHDL for Transportation Application: This project implements the PID controller for cruise system in order to avoid the collision between the vehicles. This PID controller is implemented based on Fuzzy algorithm which is simulated using VHDL language.
- Implementation of Bus Bridge between AHB and OCP: The basic idea of this project is to design a bus bridge between common and standard protocols namely Advanced High performance Bus (AHB) and Open Core Protocol (OCP) which are popular communication protocols used in System On-chip applications.
- Design of Control Area Network Protocol: This project aims to design a Controlled Area Network (CAN) protocol using Verilog HDL code by using Eight –to- Eleven modulation technique in place of conventional Software Bit Stuffing (SBS) technique.
- DMA Controller for AMBA Bus IP Core: This project gives the complete development process of DMA controller for an on-board computer using VHDL code. This FPGA based DMA controller can be useful for satellite on-board computers.
- High Precision Stepper Motor Controller Implementation on FPGA: The aim of this project is to design FPGA based stepper motor controller using VHDL code. The control function of the stepper is achieved by implementing Pulse Width Modulation technique.
- Design and Modeling of I2C Bus Controller: The
- Design of Cache Memory with Cache Controller Using VHDL: The main aim of this project is to design FPGA based cache memory for detecting the cache miss and also to implement a cache controller for tracking the cache miss in cache memory. This design is performed by mixed style of modeling in VHDL.
- An On Chip Design for Prepaid Electricity Billing System: The purpose of this circuit design is to implement an advanced and highly reliable prepaid electronic energy meter using VLSI technology. This VLSI design is implemented by ASIC design by modeling and simulating in this project.
- High Speed Network Devices Using SRL16 Reconfigurable Content Addressable Memory (RCAM): In this project, SRL16 Content Addressable Memory (CAM) unit is designed by using VHDL and FPGA technique. Compared with the traditional CAM design methods, this design gives better results in terms of parallel and fast search capabilities.
- IP-SRAM Architecture at Deep Submicron CMOS Technology : This project reduces the power dissipation in VLSI circuits by designing new SRAM architecture with IP-SRAM technique. This architecture is designed using 180nm technology.
- Glitch free NAND based Digitally Controlled Delay Line for Spread Spectrum Clock Generator: The objective of this project is to avoid the glitch problem in conventional NAND based digital control delay lines (DLDL). This project deals with the implementation of glitch free NAND based DCDL on SSGC (Spread Spectrum Clock Generator).
- Performance Analysis of Different Bit Carry Look Ahead Adder Using VHDL Environment : This project aims to design, simulate, test and implement different bit Carry Look Ahead (CLA) adder based on VHDL and to compare their results. In this 4, 8 and 16-bit CLA adders are implemented using VHDL and simulated using Modelsim software.
- High speed VLSI implementation of 256-bit Parallel Prefix Adders: This project present the new approach for the redesign of parallel prefix adders with 128 width operands of different parallel adders on Xilink Sprtan FPGA. This VLSI based design gives better performance than that of conventional adders.
- FPGA Implementation of Mutual Authentication Protocol using Modular Arithmetic: This project aims to design hardware efficient protocol for RFID system by implementing tag-reader mutual authentication scheme which is more secure for external attacks and also consumes less logic elements. This is designed by VHDL and simulated in Xilink simulator.
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